1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and more particularly, to a method of fabricating a semiconductor device that makes it possible to form via holes or contact holes in an interlevel dielectric layer in self-alignment with corresponding conductors.
2. Description of the Related Art
Recently, the integration level of Large-Scale Integrated Circuits (LSIs) has been increasing and as a result, there has been the strong need to decrease not only the size of electronic elements such as transistors to be integrated on a semiconductor substrate but also the pitch of conductive lines in each wiring layer. Thus, on designing the layout of via holes or contact holes, which are used for electrically interconnecting the conductive lines in a wiring layer with the conductive lines in an overlying wiring layer, the alignment margin of the via or contact holes has become necessary to be determined to be equal to or less than the alignment accuracy of a specific LSI fabrication system.
For example, the layout of a square via hole 152 and a conductive line 151 as shown in FIG. 1 is considered. In this case, the via hole 152 is located to entirely overlap with the vicinity of an end of the conductive line 151 in such a way that two widthwise edges 151a and 151b of the line 151 are respectively apart from corresponding or opposing edges 152a and 152b of the hole 152 at equal distances (i.e., an alignment margin) M. If the LSI fabrication system to be used has an alignment accuracy A, the alignment margin M needs to be adjusted to be equal to or less than the accuracy A, i.e., Mxe2x89xa6A.
In the explanation presented below, the term xe2x80x9cvia holexe2x80x9d means not only a via hole but a contact hole.
If the margin M is set to be equal to or less than the accuracy A, however, part of the hole 152 tends to deviate from the line 151 due to accumulation of alignment errors in the actual fabrication processes. This is explained in detail below with reference to FIG. 2.
In FIG. 2, a thin dielectric layer 161a is formed on the surface of a semiconductor substrate 161 and then, the conductive line 151 is formed on the layer 161a. A thick interlayer dielectric layer 162 is formed on the layer 161a to cover the line 151. The layer 162 has the via hole 152 that penetrates vertically the layer 162 to the line 151. Needless to say, the layout design is conducted in such a way that the hole 152 is located at the widthwise center of the line 151, as shown in FIG. 1. However, actually, the hole 152 is largely deviated from the desired or designed position due to accumulation of alignment or overlying errors among patterned masks, resulting in deviation of part of the hole 152 from the line 151, as shown in FIG. 2. In this state, as seen from FIG. 2, the upper corner and the side face of the line 151 and the dielectric layer 161a are exposed to the hole 152.
Typically, the via hole 152 is formed by selectively removing the interlayer dielectric layer 162 using a patterned resist film (not shown) in a dry etching process. Thus, if the hole 152 is deviated from the desired position, as shown in FIG. 2, not only the top surface of the line 151 but also the upper corner and side face thereof are contacted with the etching gas in the dry etching process of the layer 162 for forming the hole 152. This means that the line 151 is excessively etched in the dry etching process compared with the calculated etching amount of the line 151, thereby producing a lot of etch residues that are unable or difficult to be entirely removed. As a consequence, there arises a problem that the yield of the etching process for forming the via hole 152 is lowered. Also, since the upper corner of the line 151 is waned or cut during the etching process, there arises another problem that the electrical resistance of the resultant line 151 is higher than the desired value.
To avoid these problems, conventionally, various methods of forming the via hole 152 in self-alignment to the conductive line 151 have been developed and disclosed. One of the methods is explained below with reference to FIGS. 3A to 3D, which is disclosed in the Japanese Non-Examined Patent Publication No. 8-153796 published in June 1996.
First, as shown in FIG. 3A, a thin dielectric layer 121a is formed on the surface of a semiconductor substrate 121 that contains necessary electronic elements such as transistors therein. Next, a conductive layer (not shown) and a silicon dioxide (SiO2) layer (not shown) are successively formed on the layer 121a. These two layers are then patterned using the same resist mask, forming a conductive line 122 and a SiO2 protection layer 123 located on the line 122. The line 122 and the layer 123 constitute a lower wiring structure 130. The state at this stage is shown in FIG. 3A.
Subsequently, a silicon oxynitride (SiON) layer (not shown) is formed on the dielectric layer 121a over the whole substrate 121 and is etched back, forming a pair of SiON sidewalls 124a and 124b on the layer 121a at each side of the lower wiring structure 130, as shown in FIG. 3B.
A thick SiO2 layer 125 is formed on the dielectric layer 121a over the whole substrate 121 as an interlayer dielectric layer, as shown in FIG. 3C. The surface of the layer 125 is planarized and then, selectively removed in a dry etching process using a resist mask, thereby forming a via hole 127 to penetrate the layer 125 at a specific location. Since the SiO2 protection layer 123 of the wiring structure 130 is removed in this dry etching process, the top surface of the conductive line 122 is exposed within the hole 127. The state at this stage is shown in FIG. 3C.
The etch rate of SiON is sufficiently lower than that of SiO2 in the dry etching process for the SiO2 interlayer dielectric layer 125 and therefore, the SiON sidewalls 124a and 124b are left substantially unetched. Thus, even if the via hole 127 is laterally shifted from its desired position along the surface of the substrate 121 and part of the hole 127 deviates from the conductive line 122 due to accumulation of alignment errors among patterned masks in the actual fabrication processes, the upper corner and the side face of the line 122 is protected by the sidewalls 124a and 124b not to be contacted with the etching gas. As a result, the above-described two problems that the yield of the etching process for forming the via hole 127 is lowered and that the electrical resistance of the resultant line 122 is higher than the desired value can be avoided.
Thereafter, as shown in FIG. 3D, the via hole 127 of the interlayer dielectric layer 125 is filled with a tungsten (W) plug 123 by a known method. An upperwiring structure 131 with a specific pattern is formed on the layer 125. The plug 123 is contacted with a conductive line 126 of the structure 131. In this way, the conductive line 126 of the upper wiring structure 131 is electrically connected to the conductive line 122 of the lower wiring structure 130.
The prior-art method of fabricating a semiconductor device as shown in FIGS. 3A to 3D solves theoretically the above-described two problems. However, it does not always solve the problems in the actual fabrication processes. Specifically, in the etching process for forming the conductive line 122 and the SiO2 protection layer 123 of the lower wiring structure 130, the structure 130 does not have the vertical side faces shown in FIG. 3A but the tilted side faces shown in FIG. 4A. In other words, the structure 130 has a tapered cross section, not a straight cross section. (To facilitate understanding, the tapered shape is illustrated in FIG. 4A exaggeratingly.)
When the SiON layer 124 covering the whole substrate 121 is etched back, the layer 124 is subjected to the etching action of the active species 132, as shown in FIG. 4B. Thus, the sidewalls 124a and 124b with a extremely small thickness are formed, as shown in FIG. 4C. (To facilitate understanding, the small thickness of the sidewalls 124a and 124b are illustrated in FIG. 4C exaggeratingly.) Since these thin sidewalls 124a and 124b do not provide the desired protection action, there is a high possibility that the undesired state shown in FIG. 2 occurs in the state of FIG. 3C.
Moreover, in recent years, to planarize the surface of an interlayer dielectric layer, the Chemical Mechanical Polishing (CMP) technique has been developed and used in practice. This is because the CMP technique has an advantage that efficient surface planarization of an interlayer dielectric layer is ensured. The CMP technique is a technique that uses a proper polishing apparatus, in which a rotating polishing pad is contacted with a desired interlayer dielectric layer on the rotating semiconductor wafer under pressure while a polishing slurry is supplied to the pad.
With the CMF technique, however, the polishing rate stability is not sufficiently high and thus, there is a problem that the polishing period must be adjusted according to the state of the polishing apparatus in order to provide a desired thickness of the interlayer dielectric layer. Also, there is another problem that the polishing rate fluctuates within the surface of the substrate according to the state of the wiring structure and/or the polishing apparatus.
As a consequence, generally, it is extremely difficult to realize a desired thickness of an interlayer dielectric layer by using the CMP technique, which means that the thickness of an interlayer dielectric layer needs to be controlled by a proper measure during the CMP process. In particular, with the recent, highly-integrated LSIs, precise thickness control of an interlayer dielectric layer is essential for the CMP process for planarizing its surface, because the thickness fluctuation of an interlayer dielectric layer affects the operation speed of the LSIs.
Accordingly, an object of the present invention is to provide a method of fabricating a semiconductor device that forms dielectric sidewalls reliably at each side of a stacked structure of a conductive line and a dielectric located on the line in order to protect the conductive line in the etching process for forming a via hole in an overlying interlayer dielectric layer.
Another object of the present invention is to provide a method of fabricating a semiconductor device that makes it possible to decrease significantly the thickness fluctuation of an overlying interlayer dielectric layer.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
A method of fabricating a semiconductor device according to the present invention comprises the steps of:
(a) forming a first dielectric layer over a semiconductor substrate;
(b) forming a first wiring structure on the first dielectric layer;
the first wiring structure comprising a conductive line and a dielectric formed on the line;
(c) forming a second dielectric layer on the first dielectric layer to cover the first wiring structure;
(d) forming a third dielectric layer serving as an interlayer dielectric layer on the second dielectric layer;
(e) polishing the third and second dielectric layers using the CMP technique until the dielectric of the first wiring structure is exposed, thereby aligning a surface of the third dielectric layer with a surface of the dielectric of the first wiring structure while part of the second dielectric layer that extends along each side of the first wiring structure and a surface of the first dielectric layer is selectively left;
(f) forming a mask with a pattern for a via hole on the remaining third dielectric layer after the step (e);
(g) selectively etching the dielectric of the first wiring structure using the mask, forming a via hole that reaches the conductive line of the first wiring structure;
(h) filling a conductive plug into the via hole after removing the mask; and
(i) forming a second wiring structure on the remaining third dielectric layer or a fourth dielectric layer formed on the remaining third dielectric layer in such a way that the second wiring structure is electrically connected to the first wiring structure by way of the plug.
Furthermore, a polishing rate of the second dielectric layer in the step (e) is less than that of the third dielectric layer. An etching rate of the second dielectric layer in the step (g) is less than that of the dielectric of the first wiring structure.
With the method of fabricating a semiconductor device according to the present invention, the second dielectric layer is formed on the first dielectric layer to cover the first wiring structure and then, the third dielectric layer serving as the interlayer dielectric layer is formed on the second dielectric layer. Subsequently, the third and second dielectric layers are polished using the CMP technique until the dielectric of the first wiring structure is exposed, thereby aligning the surface of the third dielectric layer with the surface of the dielectric of the first wiring structure while the part of the second dielectric layer that extends along each side of the first wiring structure and a surface of the first dielectric layer is selectively left. Also, the etching rate of the second dielectric layer in the step (g) is less than that of the dielectric of the first wiring structure. As a result, the remaining part of the second dielectric layer that extends along each side of the first dielectric layer and the surface of the first dielectric layer can serve as protection sidewalls in the etching step (g) for forming the via hole.
Thus, the second dielectric layer is selectively left along each side of the first wiring structure by using the CMP technique instead of the etch back process causing the problems in the prior-art method. This makes sure that protective dielectric sidewalls are formed reliably at each side of the first wiring structure (i.e., the stacked structure of a conductive line and a dielectric located on the line) in the etching process for forming the via hole.
Moreover, the polishing rate of the second dielectric layer in the step (e) is less than that of the third dielectric layer and therefore, the endpoint of the polishing step (e) can be detected reliably by using the remaining second dielectric layer. This means that thickness fluctuation of the third dielectric layer serving as the interlayer dielectric layer can be significantly decreased.
Since the surface of the remaining part of the third dielectric layer is planarized after the polishing step (e), the thickness of the fourth dielectric layer located thereon is substantially uniform. Thus, the total thickness fluctuation of the remaining part of the third dielectric layer and the fourth dielectric layer can be significantly decreased.
In a preferred embodiment of the method according to the invention, the second wiring structure is formed directly on the remaining part of the third dielectric layer. The second wiring structure is electrically connected to the first wiring structure by way of the conductive plug.
In another preferred embodiment of the method according to the invention, the second wiring structure is formed over the remaining part of the third dielectric layer by way of the fourth dielectric layer. The via hole penetrates the third and fourth dielectric layers. The second wiring structure is electrically connected to the first wiring structure by way of the conductive plug.
In still another preferred embodiment of the method according to the invention, when the dielectric of the first wiring structure has a thickness of D, the thickness D is set to satisfy a specific condition. Specifically, when the third dielectric layer having an in-plane dimensional fluctuation and a polishing apparatus having an in-plane dimensional fluctuation provide a maximum, total in-plane dimensional fluctuation X, and the polishing rates of the second and third dielectric layers in the polishing apparatus are Y and Z, respectively, the thickness D satisfies an inequality of   D   greater than       X    ⁢          xe2x80x83        ⁢                  Y        Z            .      
In this preferred embodiment, there is an additional advantage that the possibility that the conductive line of the first wiring structure is exposed to be polished before the polishing process is completed on the whole substrate can be eliminated reliably.
In a further preferred embodiment of the method according to the invention, the part of the third dielectric layer located over the first wiring structure is used to detect the endpoint of the polishing step (e) In this embodiment, there is an additional advantage that the process conditions can be set easily.
In a still further preferred embodiment of the method according to the invention, the dielectric of the first wiring structure and the third dielectric layer are made of oxide of silicon and the second dielectric layer is made of nitride of silicon. In this embodiment, there is an additional advantage that the advantages of the invention are exhibited effectively.